SMTSIM

Description: University researchers have written an instruction-level simulator of a simultaneous multi-threading (also known as hyper-threading) processor. The software provides detailed simulations of a pipelined out of order processor with all sources of latency modeled. The software is compatible with Unix operating systems using a standard C compiler. A minimum of 64 Megabytes of RAM storage are recommended, along with a printer for reporting out results. Source code is available.

Keywords: processor architecture, simulation, hyper-threading

Case Number:  SD2002-810
Inquiries To:  invent@ucsd.edu