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A method to efficiently and safely signal the arrival
of incoming I/O packets in computer systems by exploiting
a standard hardware mechanism. By coordinating a program
on a host processor with the software subroutine which
controls an I/O adapter, one can exploit the "cache
invalidate" hardware mechanism to efficiently communicate
new packet arrival to the host program.
CASE NUMBER: SD2000-040
INQUIRIES TO: invent@ucsd.edu
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